Unibrain introduces USB 3.0 adapters for the professional and machine vision market, featuring Four (4) separate, independent USB 3.0, 5 Gbps channels on a single PCI-e x4 slot.
Each USB 3.0 bus takes advantages of 5 Gbps burst rate providing the ability to transfer data at ultra high speeds or get high resolution pictures at high frame rates from multiple cameras.
Unibrain Quad bus USB 3.0 Host Controller is based on Renesas uPD720202 chip and PLX PEX8608 PCI-e switch controller.
Operating system support:
Native driver support for Windows 8 & 10.
For Windows 7 only, Download Renesas Driver (For Windows 8/10 the native driver should be used).
Linux (Kernel 2.6.31 or later).
The Dual bus USB 3.0 card has been discontinued
- Two/Four separate USB 3.0 buses.
- Two/Four independent 5 GT/sec (500 MBytes/sec) PCI-e v2.0 lanes.
- Two USB 3.0 port for each bus on the Dual bus adapter.
- One USB 3.0 port for each bus on the Quad bus adapter.
- Internal power connector (4 pin, ‘big’ IDE) for extra power stability.
- Legacy connectivity support for USB 2.0 devices.
- RoHS and WEEE compliant.
- Operating Temperature: 0~65′ C, Storage Temperature: -20 ~ 100′ C.
- Humidity Operating: 0 ~ 80% RH, Non-condensing.
μPD720202 Renesas’ third generation Universal Serial Bus 3.0 host controller:
- Compliant with Universal Serial Bus 3.0 Specification Revision 1.0, which is released by USB Implementers Forum, Inc.
- Supports the following speed data rates: Low-Speed (1.5 Mbps) / Full-Speed (12 Mbps) / Hi-Speed (480 Mbps) / SuperSpeed (5 Gbps)
- μPD720202 supports up to 2 downstream ports for all speeds
- Supports all USB compliant data transfer types as follows; Control / Bulk / Interrupt / Isochronous transfer
- Compliant with Intel’s eXtensible Host Controller Interface (xHCI) Specification Revision 1.0
- Supports USB legacy function
- Compliant with PCI Express Base Specification Revision 2.0
- Supports Latency Tolerance Reporting ECN of PCI Express Specification
- Supports PCI Express Card Electromechanical Specification Revision 2.0
- Supports PCI Bus Power Management Interface Specification Revision 1.2
- Operational registers are direct-mapped to PCI memory space