Open Host Controller Interface (OHCI)

• Enhanced with the 1394 OHCI 1.2 draft specification for 1394b Phy full operational compliance.
• OHCI 1.0 backwards compatible.
• Isochronous receive dual-buffer mode.
• Supports enhanced isochronous transmit skip/overflow.
• Enhanced CSR (configuration status register) implementation.
• Autonomous configuration ROM update.
• Enhanced power management support.
• Enhanced self-ID protocol including selfIDComplete2 event.
• Enhanced FIFO characteristics:
• 8 Kbyte isochronous transmit FIFO.
• 4 Kbyte asynchronous transmit FIFO.
• 8 Kbyte isochronous receive FIFO.
• 8 Kbyte asynchronous receive FIFO.
• Dedicated asynchronous and isochronous descriptor-based DMA engines.
• Eight isochronous transmit contexts.
• Eight isochronous receive contexts.
• Prefetches isochronous transmit data.
• Supports posted write transactions.
• Supports parallel processing of incoming physical read and write requests.
• Allows multiple outstanding requests at DMAs.
• Segments transfers into PCI Express-sized requests.

1394b integrated Bilingual Phy and Link

• Cycle master and isochronous resource manager capable.
• Supports 1394a-2000 and 1394b acceleration features.
• Fully supports provisions of IEEE 1394a-2000 and 1394-1995 standard for high-performance serial bus.
• Supports registers to indicate power class modes.
• Supports arbitrated short bus reset to improve utilization of the bus.
• Supports ack-accelerated arbitration and fly-by concatenation.
• Supports connection debounce.
• Supports multispeed packet concatenation.
• Supports Phy pinging and remote Phy access packets.
• Fully supports port disable/suspend/resume.
• Supports Phy-link interface initialization and reset.
• Fully interoperable with Firewire™ and i.LINK® implementation of IEEE 1394-1995.

PCI Express

• Full compliance with PCI Express revision 1.1.
• Single lane (x1) architecture.
• Multiple virtual channel (VC0 and VC1) support for differentiating 1394 isochronous traffic.
• Supports eight user-programmable traffic classes.
• Interrupts via legacy INTx interface or message signalled interrupt (MSI).
• Supports advanced error reporting (AER).
• Supports multiple concurrent transactions for optimum bandwidth utilization.
• Supports 64-bit and 32-bit platforms.
• Supports active-state power management (ASPM).
• Integrated 2.5 Gbits/s SerDes for serial data transfer.
• Supports all power management link and device states: L0, L0s, L1, L2/L3, D0, D1, D2 and D3.
• Low power consumption in and fast transition out of a low-powered Rx mode.
• Low power consumption in Tx electrical idle.
• Supports in-band beacon transmission and side-band WAKE_N signaling mechanism.
• Both Tx and Rx termination impedances are automatically calibrated using an external reference resistance.
• Supports Type 0 (endpoint) PCI-compatible configuration space and PCI Express extended configuration space.